By reasonably using the special resources in FPGA, such as DCMs ( Digital Clock Manager) and BUFGMUXBy reasonably using the special resources in FPGA, such as DCMs ( Digital Clock Manager) and BUFGMUX
通过合理使用DCM（数字时钟管理单元）和BUFG-MUX（全局时钟选择缓冲器）等FPGA的特殊资源，手动搭建时钟电路，可以尽可能地减少时钟偏差对电路时序的影响。
World Clock plug-in – new analog clock faces and new digital clock design.World Clock plug-in – new analog clock faces and new digital clock design.
世界时钟插件-新的模拟时钟的面孔和新的数字时钟设计。
At last, the application of individual digital clock reconnaissance systems in anti-terrorism combatAt last, the application of individual digital clock reconnaissance systems in anti-terrorism combat
因此，研究数字钟及扩大其应用，有着非常现实的意义。
As a result, digital clock and the expansion of its application, has a very real sense.As a result, digital clock and the expansion of its application, has a very real sense.
结合嵌入式系统课程的特点，并以数字时钟的设计为例，介绍了将建构主义教学理论应用于嵌入式系统课程教学。
Combining the Constructivism Ideology and taking the case of digital clock design, this paper presenCombining the Constructivism Ideology and taking the case of digital clock design, this paper presen
那台数字显示式时钟上的时间不准确。
The digital clock showed the wrong time.The digital clock showed the wrong time.
VHDL编写。在CPLK开发板上设计的数字钟的去抖动电路。
Research and trial operation on the seismic digital clock地震专用数字钟的研制及试运行结果23、World Clock plug-in – neResearch and trial operation on the seismic digital clock地震专用数字钟的研制及试运行结果23、World Clock plug-in – ne
地震专用数字钟的研制及试运行结果
A debouncing circuit which is part of a digital clock designed on a CPLD development board.A debouncing circuit which is part of a digital clock designed on a CPLD development board.
世界时钟插件-新的模拟时钟的面孔和新的数字时钟设计。
It has digital clock, calendar and note's area for every day.It has digital clock, calendar and note's area for every day.
有数字时钟，日历和注意的地区，每一天。
The Design of a Multifunctional digital clock Based on MCUThe Design of a Multifunctional digital clock Based on MCU
基于单片机的多功能数字时钟系统设计分析
